Hardware Architecture

This section introduces the hardware structure of the REDAC analog computer family. It explains how the system is built from repeated computation clusters, how those clusters are combined into mREDAC modules, how multiple mREDACs form an iREDAC stack level, and how several iREDACs are assembled into a complete REDAC rack.

The documentation is intended for readers who want to understand the hardware-level signal path, routing structure, and main building blocks used by REDAC systems. It complements the pybrid configuration model by showing what the software configures in hardware: source selection, coefficient paths, summing stages, Math Block positions, topology routing, synchronization, and rack-level interconnection.

Start with Hierarchy: From Cluster to the REDAC for the structural overview. Then use List of Blocks and the individual block pages for detailed descriptions of each hardware block and its role in the analog signal flow.